| 摘要 |
PURPOSE:To reduce power consumption of a circuit employing EPROMs or EEPROMs by delivering a chip enable signal to the memory only during an interval when any one of output enable signal or write enable signal, being inputted to the memory, is active. CONSTITUTION:A NAND circuit 4A inserted between memories 1 and 2 has an input terminal receiving an output enable signal OE and a write enable signal WE. An OR circuit 5a has an input terminal receiving an output signal from the circuit 4a and a signal A19 from a CPU 1 and an output terminal connected with the chip enable signal CE terminal of the memory 2. The circuits 4a, 5a constitute a circuit 6 for reducing current consumption of the memory. Output signal from the circuit 4a goes 'L' when the signal OE or WE is 'L' and the logical sum of that signal and the signal A19 can be produced from the circuit 5a and thereby the chip enable signal can be brought into 'L' level. |
