| 摘要 |
The method includes the steps of forming a tunnel oxide film (2) on the substrate (1) to deposit a 1st conducting layer (3) to form a floating gate pattern, forming an interlayered insulating layer (4) and a 2nd conducting layer (5) thereon to etch the layers (5,4,3) to form a memory cell, depositing insulating layers (7,8,9) thereon to etch-back the layer (9) to form a spacer (9') on the side wall of the cell to etch the exposed layer (8), implanting P type impurities to remove the spacer to form a mini field oxide film (11), and implanting n-type impurities to form a source region to deposit and etch-back a 3rd conducting layer (12) thereon to form a source line (12).
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