发明名称 CLOCK DUTY VARIABLE CIRCUIT
摘要 <p>PURPOSE:To constitute the duty variable circuit which is irrespective of magnitude of an input clock, and also, whose operation frequency is wide, of a simple circuit. CONSTITUTION:This circuit is constituted in such a manner that an FF 1 is set by a rise of an input clock, its output is converted to a lamp voltage by an integration circuit 2, compared with a set value of a comparator 3 and when the former exceeds, the FF 1 is reset by an output of the comparator 3 and pulse width is obtained. Also, a part of the output of the FF 1 is converted to a DC voltage by an LPF 4, difference from a reference voltage Vr (adjustable) is taken by a differntial amplifier circuit 5, and by a difference output, a time constant of the abovementioned integration circuit 2 is varied. In this regard, a diode 6 is provided between the output side of the FF1 and an output of the integration circuit 2, and when the lamp voltage exceeds a set number of the comparator 3, the output of the FF 1 becomes a low level and electric discharge is executed through the diode 6.</p>
申请公布号 JPH077396(A) 申请公布日期 1995.01.10
申请号 JP19930172332 申请日期 1993.06.18
申请人 JAPAN RADIO CO LTD 发明人 MAKISHIMA YOJI
分类号 H03K5/04;H03K5/13;(IPC1-7):H03K5/13 主分类号 H03K5/04
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