TIME BASE CORRECTING DEVICE

摘要

PURPOSE:To reduce the scale of a time base correcting circuit by enabling a memory to be variable the phase relation between the writing timing of data and the reading timing thereof in a certain degree. CONSTITUTION:A clock and a reference signal whose phase is synchronized with that of a horizontal synchronizing signal is outputted from a Hi-PLL circuit in a clock and reference signal generating circuit 10. An ADC 1 converts an input signal into a digital signal by using a clock outputted from the circuit 10. A control circuit 5 generates a write control signal for an FIFO 3 in accordance with the 1st clock and a horizontal reference signal outputted from the circuit 10. A data processing circuit 2 executes the data processing of the input signal in accordance with the control signal generated from the circuit 5 and writes the processed data in the FIFO 3. The circuit 5 outputs also reference signal for determining the reading timing of the FIFO 3. Reading from the FIFO 3 and writing in a picture memory 4 are a series of operation and processed by the 2nd clock generated by a Lo-PLL in the circuit 10. Thereby a conversion circuit 6 synchronizes the FIFO reading reference signal outputted from the circuit 5 with I/O operation in/from the memory 4.