| 主权项 |
1. A semiconductor device comprising
a NAND decoder including six transistors, each having a source, a drain, and a gate arranged in a layered manner in a direction perpendicular to a substrate, the six transistors being arranged on the substrate in a line in a first direction, each of the six transistors including
a silicon pillar,an insulator that surrounds a side surface of the silicon pillar,a gate that surrounds the insulator,a source region disposed in an upper portion or a lower portion of the silicon pillar, anda drain region disposed in the upper portion or the lower portion of the silicon pillar, the drain region being located on a side of the silicon pillar opposite to a side of the silicon pillar on which the source region is located, the six transistors including
a first p-channel MOS transistor,a second p-channel MOS transistor,a third p-channel MOS transistor,a first n-channel MOS transistor,a second n-channel MOS transistor, anda third n-channel MOS transistor, the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor being connected to each other, the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor being connected to each other, the gate of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor being connected to each other, the drain regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first re-channel MOS transistor being located closer to the substrate than the silicon pillars of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor, respectively, and being connected to one another to form an output terminal, the source region of the second n-channel MOS transistor and the drain region of the third n-channel MOS transistor being located closer to the substrate than the silicon pillars of the second n-channel MOS transistor and the third n-channel MOS transistor, the source region of the first n-channel MOS transistor being connected to the drain region of the second n-channel MOS transistor, the source region of the second n-channel MOS transistor being connected to the drain region of the third n-channel MOS transistor, the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, and the third p-channel MOS transistor being connected to a power supply line, the source region of the third n-channel MOS transistor being connected to a reference power supply line, the decoder further including
a first address signal line,a second address signal line, anda third address signal line, the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor, which are connected to each other, being connected to the first address signal line, the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor, which are connected to each other, being connected to the second address signal line, the gate of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor, which are connected to each other, being connected to the third address signal line, the power supply line, the reference power supply line, the first address signal line, the second address signal line, and the third address signal line being arranged to extend in a second direction perpendicular to the first direction. |
