| 摘要 |
<p>PURPOSE:To obtain a clock signal distribution system where the delay difference in a clock signal is reduced and degree of integration is increased without using extra wirings within an integrated circuit. CONSTITUTION:Wirings 4c and 4d between a clock signal output circuit 2 and each clock signal input circuit are reduced delay blocks 5a and 5b for compensating a delay difference caused accordingly are provided at each clock signal input circuit.</p> |
