| 摘要 |
<p>PURPOSE:To provide an elastic memory circuit which can be immediately operated in a stable operating state at the time of recovery to a normal operating state and can suppress the increase of output jitter at a path terminating point while decreasing useless stuff sending operations. CONSTITUTION:A write address counter 2 generates a write address S7. On the other hand, a read address counter 3 generates a read address S8. A memory circuit 1 is provided for storing write data S1, LOP detect signal S2 and P-AIS detect signal or the like, stores data in a storage area designated by the write address S7 and outputs data in a storage area designated by the read address S8. In a warning state (in the state of inputting a P-AIS transmission control signal S6), the write address counter 2 and the read address counter 3 preset the write address S7 and the read address S8 at respectively different prescribed values.</p> |
