| 摘要 |
<p>PURPOSE:To improve the operation speed even when the load capacity is large by providing plural buffer circuits, and inputting and outputting the output signal of a differential amplification part as a signal for latching by one buffer circuit. CONSTITUTION:A latch circuit 100 latches and amplifies input signals 3 IN and/IN in synchronism with a clock signal CK/CK, and outputs them as output signals OUT and/OUT. Then the differential amplification part 103 inputs and latches the signal for latching and sends its output signal to the buffer circuits 104 and 105. Here, the circuit 104 outputs output signals OUT and/OUT and the buffer circuit 105 inputs the output signal of the amplification part 103 and feeds it back to the amplification part 103 as the signal for latching. Then the additional capacity between the output of the precedent latch circuit and following latch circuit 100 is reducible.</p> |
