| 摘要 |
<p>A circuit for translating logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail in which the potentials of the two high-potential rails are not equal. The translator of the present invention is utilized in the transition from a 3V-supplied circuit to a 5V-supplied circuit, or vice versa, without any static current ICCt and regardless of the power-up sequencing. The static current is eliminated by isolating the output of the first stage (11) of the translator, which is at the first high-potential power rail level VCCA, from all transistors of the second stage (12) that are tied directly to the second high-potential power rail VCCB. In the preferred embodiment of the invention the transistors of the second stage that are powered by the second high-potential power VCCB rail are PMOS transistors (PB1, PB2, PB3) and the isolation is achieved by linking those PMOS transistors to the first stage (11) through a series of controlling NMOS transistors (NB1, NB2, NB3). In that way, the PMOS transistors will be completely turned off when necessary so as to avoid any undesirable conduction paths occurring due to differences in the potentials of the two high-potential power rails.</p> |
