| 摘要 |
<p>PURPOSE:To allow the clock skew to a very low level by connecting a clock wiring, at one end thereof, with a clock driver and terminating the other open end. CONSTITUTION:A main clock wiring 1 has one open end 2 and the other end 3 connected with the output terminal of a clock buffer 4. A clock signal fed to the input terminal 3 of the basic clock wiring 1 is reflected at the terminal 2 and advances reversely at the same speed as the incident wave. Assuming that the transmission loss of the basic clock wiring 1 is zero and the reflectance is 1, the incident wave is combined with the reflected wave and the clock skew in the main clock wiring 1 becomes substantially zero. Consequently, when the wiring 7 to each flip-flop 6 is started from a clock signal wiring 8, the clock skew is equal to the time lag caused by the imbalance between the resistance and capacitance of a wiring 7 and a clock signal branch wiring 8 and the total input capacitance of flip-flops 6 connected to the terminals 9.</p> |
