PHASE LOCKED LOOP OSCILLATION CIRCUIT

摘要

PURPOSE:To generate a stabilized clock signal synchronously with a main station side clock signal from a subordinate station of a synchronization multiplex transmission system by obtaining an output signal in following to a phase and a frequency of an input signal. CONSTITUTION:An input stage phase locked loop circuit 2 uses a 1st phase comparator circuit 1, compares a phase of an input signal with a phase of a 1st frequency conversion output signal of a frequency conversion section 6 and an output signal of the comparator circuit 1 controls the conversion section 6 to synchronize the 1st frequency conversion output signal with the phase of the an input signal. An arithmetic processing section 3 obtains the frequency component of the input signal based on the output signal of the circuit 1. An output stage phase synchronization circuit 5 compares the phase of the input signal with that of a 2nd frequency conversion output signal of a frequency conversion section 7. The processing section 3 controls the conversion section 7 with a frequency component of the input signal and controls the phase of the frequency change output phase signal with a phase comparison output signal of a 2nd phase comparator circuit 4. That is, the circuit 2 synchronizes the 1st frequency conversion output signal with the frequency of the input signal and the circuit 5 synchronizes the phase of the 2nd frequency conversion output signal with the phase of the input signal.