| 摘要 |
PURPOSE:To enable testing of a high speed memory by installing a plural number of PG (Algorithmic pattern generating unit) and a multiplexer (MUX). CONSTITUTION:An algorithmic pattern generating device is composed of PG1-PG3 and MUX13. In the PG1, an algorithmic pattern 17 is output from an ALPG (Algorithmic pattern generator) 1 by a microprogram controlling system and stored in a PDB (Memory) 4. In the PDB4, the address is specified by a counter 10 and the counter 4, the ALPG1 and a MUX13 are controlled by a CTL (controlling circuit) 7. Further, a low speed clock 44 and a high speed clock 45 are selectively input from the outside and are used for WRITE and READOUT. By switching the MUX13 successively with the output from the PDB4-6, the output of the algorithmic pattern can be obtained at the READOUT speed of the PDB4-6 continuously. |
