| 摘要 |
<p>PURPOSE:To provide a clock reproduction system/circuit by which a device can be miniaturized, cost and power consumption can be reduced and a phase jitter can bee reduced in a high speed system. CONSTITUTION:A timing extractor 1 extracts a timing signal corresponding to the speed of data from inputted data. A phase comparator 2 detects a phase difference with a reproduced clock and an integrator 4 integrates a phase difference signal from which high frequency noise is removed by a filter 3. Table data for reproducing a sine waveform is recorded in ROM 5. Sampling data of the sine waveform is read with integrated data as an address, and a D/A converter 6 converts it into an analog signal. The reproduced sine waveform of the analog signal, which is made a basic wave in a filter 7, is compared with reference voltage by a comparator 8, and it is set to be the reproduced clock. The reproduced clock by a PLL circuit is generated from the analog signal and therefore the resolution of speed is not restricted by the speed of FASTCLK.</p> |
