| 摘要 |
PURPOSE:To places a stand-by system clock signal in a state wherein operation guarantee width is guaranteed without generating any hazard and switches it to an in-use system clock signal in an excellent state irrelevantly to any phase difference between two kinds of clock signal. CONSTITUTION:One of the clocks CK0 and CK1 is selected and outputted if the phase difference between the clock signals CK0 and CK1 is not inverted, and one of the CK0 and delay CK1 is selected and outputted if one of the clock CK0 and CK1 is inverted by a selector 26 according to the signal state of a signal CLKSEL, but when the CLKSEL is inverted, the pulse signal with the operation guarantee width which is generated by a generator 28 is ORed with the output of the selector 26. |
