| 摘要 |
a presum stage for generating a carry signal by a logical multiplier which outputs '1', when input signals are '1', for generating a precharge signal by a logical summer which outputs '1', when one of the input signals is '1', and for generating a presum signal by an exclusive logical summer which outputs '1', when one of the input signals is '1'; a sum select stage for receiving the precharge signal, the carry signal and the presum signal from the presum stage and a carry signal from a prestage, to generate a carry output signal to next stage and output a sum select signal; and a multiplexor for receiving the presum signal from the presum stage and the sum select signal from the sum select signal.
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