发明名称 ARRAY ARCHITECTURE WITH ENHANCED ROUTING FOR LINEAR ASICs
摘要 <p>A linear, bipolar-type application-specific integrated circuit includes a silicon substrate having a plurality of columns of device primitives or cells. Each cell comprises a plurality of identical NPN and PNP transistors flanking a centrally-located capacitor. Each transistor has dual emitters, bases and collectors. Open field areas are reserved on the silicon substrate on the sides of the columns of cells. Formed in these open field areas are precise thin film silicon chromium resistors. Power planes are also routed in these open field areas. A ground plane is routed in the vicinity of the centrally-located capacitor. Standard analog circuits are personalized using two layers of metallization interconnects.</p>
申请公布号 WO1995027311(P1) 申请公布日期 1995.10.12
申请号 US1995004053 申请日期 1995.03.30
申请人 发明人
分类号 主分类号
代理机构 代理人
主权项
地址