发明名称 TESTING SYSTEM FOR COMPUTER
摘要 PURPOSE:To test the fine fault processing. CONSTITUTION:A software interface part 21 or a fault set control part 2 switches a selector 22 to set the count value indicating the time zone, when a pseudo fault is brought about to a counter 23. After setting of the count value is terminated, the software interface part 21 switches the selector 22 to input the output of a subtractor 24 to the counter 23. The count value of the counter 23 is decreased one by one by the subtractor 24. An OR gate 25 operates OR among respective bits of the output of the counter 23 and outputs the operation result to a decoder 16 through an OR gate 15. The decoder 16 is effective until the count value set to the counter 23 reaches 0.
申请公布号 JPH0844584(A) 申请公布日期 1996.02.16
申请号 JP19940180132 申请日期 1994.08.01
申请人 NEC ENG LTD 发明人 HIRAYAMA SHUYA
分类号 G06F11/22 主分类号 G06F11/22
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