| 摘要 |
PURPOSE:To make the synchronization of a phase locked loop circuit stable and to use the circuit for generating time data. CONSTITUTION:Information PCR being time and phase information and a count from a counter 213 are given to a subtractor 210, from which the difference is fed to a VCXO 212 via an LPF 211 to control a frequency and a phase of an output clock. Then an output of the subtractor 210 is given to a comparator 214, in which the output is compared with a fixed value, and the PCR is loaded to the counter 213 when the difference is larger than a prescribed value thereby suppressing a large fluctuation in an output of the subtractor 210 and obtaining an instantaneous phase lock state. Furthermore, the output of the counter 213 is converted into time information by a time conversion circuit 216. |
