发明名称 CPU APPLICATION CIRCUIT
摘要 <p>PURPOSE: To continue a stable operation by preventing it that a peripheral circuit is reset due to a noise signal or the like intruded on a reset signal line. CONSTITUTION: In the CPU application system including a CPU 1 and a CPU peripheral circuit 3, and in the CPU application circuit where the CPU 1 and the CPU peripheral circuit 3 are reset by a reset signal from a reset circuit 2 generating the reset signal, the supply of the reset signal to the CPU peripheral circuit 3 is conducted by providing a reset time control circuit 5 which generates a reset signal for the peripheral circuit continuously over a time required at least for the CPU 1 to be transited to the reset operation and provides the reset signal to the CPU peripheral circuit 3.</p>
申请公布号 JPH0869345(A) 申请公布日期 1996.03.12
申请号 JP19940203765 申请日期 1994.08.29
申请人 TOSHIBA CORP 发明人 TAKATSUKI EIICHIRO
分类号 G06F1/24;(IPC1-7):G06F1/24 主分类号 G06F1/24
代理机构 代理人
主权项
地址