| 摘要 |
PURPOSE: To reduce the area and power consumption of a circuit for synchronizing data signals by synchronizing a feedback clock to a reference clock by making the frequency of a reference clock signal equal to that of a controller chip and also synchronizing data signals to the reference clock by latching the data signals with the feedback clock. CONSTITUTION: A synchronizing circuit 30 fetches a reference clock signal CLKref and a dividing circuit 32 divides the frequency of the signal CLKref to the same frequency as that of a feedback clock signal CLKin . A PLL 34 receives the output of the circuit 32 and the signal CLKin and synchronizes its output clock signal CLKout to the output of the circuit 32. The PLL 34 obtains synchronization between a changed reference clock signal CLKref and the feedback clock signal CLKin by adjusting the phase of the signal CLKin by adjusting the frequency of the signal CLKout . Then the signal CLKout is fed back to a controller chip and the chip adds various delays to the signal CLKout . Therefore, the output of the PLL 34 is synchronized to the reference clock signal CLKref and, accordingly, data are synchronized to the signal CLKref . |
