| 摘要 |
<p>PURPOSE: To output highly accurate pulse signals by providing first and second registers and first and second matching circuits, changing a second value stored in the second register and arbitrarily controlling the output timing of third signals. CONSTITUTION: A counter 1 inputs clocks CLK and counts them. A matching circuit 2 detects whether or not a value stored in a register 3 matches the value counted by the counter 1, and when they match, outputs matching signals to the reset terminal R of an FF 4. The matching circuit 5 detects whether or not the value stored in the register 6 matches the value counted by the counter 1, and when they match, outputs interruption request signals. The FF 4 outputs the PWM pulses for controlling an external equipment of a cycle corresponding to the overflow output of the counter 1 and the matching signals from the matching circuit 2 by outputting H when pulses are inputted to a set terminal S and outputting L when the pulses are inputted to the terminal R.</p> |
