| 摘要 |
<p>PURPOSE: To provide a nonvolatile memory device in which the layout of decoder elements is suited for the fining of memory cells and capable of a high speed operation. CONSTITUTION: In a word decoder circuit hierarchized for attaining the speeding up, one decoder element is shared with word lines of n rows by providing selectively selectable switches (for example, SW00, SW01) in between the output of each decoder (for example, SD0) and word lines of n rows (for example, W00, W01). By such a constitution, the layout pitch of decoder elements is made to be n times of the pitch of word lines. Moreover, decoder elements are reduced with respect to the number of word lines and wirings in a word line direction are also reduced. Thus, the nonvolatile memory suitable for the speeding up and simultaneously suitable to make memory cells fine is realized.</p> |
