Method and apparatus for power conservation in LDPC decoding

摘要

There is provided, in accordance with an embodiment, a method of decoding codewords in conjunction with a low-density parity-check (LDPC) code that defines variable nodes and check nodes, the method comprising receiving a codeword over a data channel; evaluating quality of the data channel; and iteratively updating values of the variable nodes to decode the codeword; wherein the values of the variable nodes are updated at different levels of numeric precision depending on the evaluated quality of the data channel.

主权项

1. A method of decoding codewords in conjunction with a low-density parity-check (LDPC) code that defines variable nodes and check nodes, the method comprising:
receiving a codeword over a data channel; evaluating quality of the data channel; iteratively updating values of the variable nodes to decode the codeword, wherein the values of the variable nodes are updated at different levels of numeric precision depending on the evaluated quality of the data channel, wherein a first one or more registers are associated with processing high-order bits of the values of the variable nodes, and wherein a second one or more registers are associated with processing low-order bits of the values of the variable nodes; storing the values of the variable nodes in a memory, wherein the memory is partitioned in a first memory and a second memory, wherein the memory is different and separate from the each of (i) the first one or more registers and (ii) the second one or more registers, wherein the first memory is configured to store the high-order bits of the values of the variable nodes and the second memory is configured to store the low-order bits of the values of the variable nodes; and in response to the evaluated quality of the data channel being greater than a predetermined threshold, disabling (i) the second one or more registers and (ii) the second memory.