Circuitry and methods for measuring and correcting duty-cycle distortion

摘要

A method of measuring duty-cycle distortion in a signal (e.g., flowing between an operating circuit and a memory circuit), where the signal has a known period, the signal being measured is in a first state during a first portion of the period, and is in a different state during a second portion of the period, includes advancing or retarding the signal until an edge of the signal intersects an edge of the other signal. From the amount of the advancing or retarding, the duty cycle and the magnitude of duty-cycle distortion are determined. This may be used to control correction of the duty-cycle distortion. An interpolator circuit may be used to advance or retard the signal. A processor may be used to keep track of the amount of advancing or retarding, to determine the duration of the duty cycle, and control correction of the duty-cycle distortion.

主权项

1. A method of measuring duty-cycle distortion in one of a clock or data signal, wherein:
said clock signal and said data signal have a known period; said one of said data signal and said clock signal is in a first state during a first portion of said known period, and is in a second state, different from said first state, during a second portion of said known period, wherein said first state is HIGH and said second state is LOW; said method comprising:
advancing or retarding said one of said clock or data signal until an edge of said one of said clock or data signal intersects an edge of another of said clock or data signal, and keeping track of an amount of said advancing or retarding until said edge of said one of said clock or data signal intersects an edge of another of said clock or data signal, wherein said advancing or retarding said one of said clock or data signal until an edge of said one of said clock or data signal intersects an edge of another of said clock or data signal comprises advancing or retarding said one of said clock or data signal until an edge of said portion of said one of said clock or data signal in said first state or said second state intersects a rising edge or a falling edge of said another of said clock or data signal;deriving from said amount of said advancing or retarding a duration of a portion of said one of said clock or data signal;determining from said duration a duty cycle of said one of said clock or data signal; andcomparing said duration of a duty cycle to an expected duty cycle.