发明名称 SWITCHING DEVICE FOR DIGITAL DATA NET
摘要 <p>PROBLEM TO BE SOLVED: To obtain an ATM switch with a small input and output number with a structure much more adaptive to the use of an integrated circuit. SOLUTION: All the required storage buffer areas are in existence in a memory 1 used in common for all input and output channels 24, 25, and the connection between the channel and the memory 1 is established by a synchronization bus 3. A time assignment on the bus 3 is designed over a wide band network such that a sufficient time slice for transfer of complete data cells between an input or output and the memory 1 is assigned to each input and output within a transmission time of the data cells according to the ATM reference, for example. The memory 1 is divided fixedly to a buffer area of the same size. Through the simple time assignment of the bus 3 in this way, pluralities of input and output channels are combined with input/output units 5, 6. A low price standard memory device is used for the memory 1.</p>
申请公布号 JPH08195757(A) 申请公布日期 1996.07.30
申请号 JP19950176293 申请日期 1995.07.12
申请人 ASUKOMU TEKU AG G FUER IND FORSCH & TEKUNOROJIEN DER ASU COM 发明人 ANDORE JIRAARU;REINAA FUAARU
分类号 H04Q3/00;H04L12/54;H04L12/933;H04L12/935;H04Q3/52;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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