发明名称 NORMALIZED DATA GENERATION CIRCUIT
摘要 PURPOSE: To provide a normalized data generation circuit which can increase its working speed by outputting the information showing the distance between the decimal point position and the bit position of the input data and then shifting the input data. CONSTITUTION: A normalized data generation circuit is provided with an information output means 1 which detects the position where the bit having its logical state different from the head bit of the input data appears first toward the lower rank side and outputs the information showing the distance between the decimal point position and the bit position of the input data, and a shift means 2 which shifts the input data based on the output of the means 1. Then it is presumed that the input data are equal to '0000. 00010000', for example, where the period shows the decimal point position. Under such conditions, the bit ('1') having its logical state different from the head bit of the input data appears first toward the lower rank side at the 8th bit from the higher rank side together with the position distant from the decimal point position set at '3' when the fist place of the decimal point position is set at '0'. Thus it is possible to obtain the normalized data '0000. 10000000' by shifting left the input data by 3 bits through the means 2.
申请公布号 JPH08212052(A) 申请公布日期 1996.08.20
申请号 JP19950016320 申请日期 1995.02.03
申请人 FUJITSU LTD 发明人 KASUYA TAKESHI
分类号 G06F7/00;G06F5/01;G06F7/76 主分类号 G06F7/00
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