| 摘要 |
<p>PURPOSE: To decrease the leakage current of a polycrystalline silicon TFT by relatively determining the values of the capacitance between light shielding films and respective inter- electrode wirings and between pixel electrodes in such a manner that the potential of the light shielding films enter in the range of the specific min. potential of the light shielding films. CONSTITUTION: The light shielding films 8 are formed separately by each of respective pixels and are insulated and are provided with the overlaps with insulating films 7 between the light shielding films 8 and gate electrodes 1a wirings, between the light shielding films 8 and source electrode wirings 3 and between the hight shielding film 8 and the pixel electrode 4. The capacitance between the light shielding films 8 and the gate electrode wirings is defined as C1 , the capacitance between the light shielding films 8 and the source electrode wirings 3 as C2 and the capacitance between the light shielding films 8 and the pixel electrodes 4 as C3 . The values of C1 to C3 are then relatively determined in such a manner that the potential VB of the light shielding films enters in the range of VBMIN±2V if the potential VB of the light shielding films at which the parasitic channel current of the polycrystal semiconductor TFTs is nearly minimized is defined as the min. potential VBMIN of the light shielding films at the time the thin-film transistors (TFTs) is brought into a non-selection state by impression of the max. effective voltage between the sources and the drains and impression of the off voltage on the gate electrodes 1.</p> |
