发明名称 POWER CONSUMPTION REDUCTION SYSTEM OF DATA PROCESSOR
摘要 <p>PURPOSE: To lower the power consumption more surely and efficiently than conventional one. CONSTITUTION: This system has a keyboard 4, a switch circuit 5, a storage part 2, a processor 1 which executes a program stored in the storage part 2, a flip-flop 11 and a flip-flop 12 which can be set and reset by the processor 1, and a clock control circuit 3 which varies the frequency of a clock according to logical values of the flip-flops 11 and 12. The processor 1 sets the flip-flop 12 when the idling routine of the program in the storage part 2 is passed through and resets the flip-flop 12 when the routine is exited from. The frequency of the clock can be varied by the switch circuit 5 or even through external operation on a keyboard.</p>
申请公布号 JPH08241145(A) 申请公布日期 1996.09.17
申请号 JP19950066665 申请日期 1995.03.02
申请人 NEC CORP 发明人 YASUE KAZUO
分类号 G06F1/04;(IPC1-7):G06F1/04 主分类号 G06F1/04
代理机构 代理人
主权项
地址