| 发明名称 |
SEMICONDUCTOR STRUCTURE AND ETCH TECHNIQUE FOR MONOLITHIC INTEGRATION OF III-N TRANSISTORS |
| 摘要 |
Semiconductor structures are disclosed for monolithically integrating multiple III-N transistors with different threshold voltages on a common substrate. A semiconductor structure includes a cap layer comprising a plurality of selectively etchable sublayers, wherein each sublayer is selectively etchable with respect to the sublayer immediately below, wherein each sublayer comprises a material AlxInyGazN (0≦x, y, z≦1), and wherein at least one selectively etchable sublayer has a non-zero Ga content (0<z≦1). A gate recess is disposed in a number of adjacent sublayers of the cap layer to achieve a desired threshold voltage for a transistor. Also described are methods for fabricating such semiconductor structures, where gate recesses and/or ohmic recesses are formed by selectively removing adjacent sublayers of the cap layer. The performance of the resulting integrated circuits is improved, while providing design flexibility to reduce production cost and circuit footprint. |
| 申请公布号 |
US2016300835(A1) |
申请公布日期 |
2016.10.13 |
| 申请号 |
US201615094985 |
申请日期 |
2016.04.08 |
| 申请人 |
Cambridge Electronics, Inc. |
发明人 |
Xia Ling;Azize Mohamed;Lu Bin |
| 分类号 |
H01L27/088;H01L21/8252;H01L29/778;H01L29/423 |
主分类号 |
H01L27/088 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A multi-layer semiconductor structure for integrating III-Nitride (III-N) transistors with different threshold voltages, comprising:
a common substrate; a buffer layer disposed on the common substrate, the buffer layer comprising a first III-N material; a channel layer disposed on the buffer layer, the channel layer comprising a second III-N material; a band-offset layer disposed on the channel layer, the band-offset layer comprising a third III-N material; a cap layer comprising a plurality of selectively etchable sublayers, wherein each sublayer is selectively etchable with respect to a sublayer immediately below, wherein each sublayer comprises a III-N material AlxInyGazN (0≦x, y, z≦1), and wherein at least one of the plurality of selectively etchable sublayers has a non-zero Ga content (0<z≦1); a first transistor with a first threshold voltage VT1, comprising a first gate region and a first pair of ohmic contacts disposed outside the first gate region, wherein the first gate region comprises a first gate recess disposed in a first number of adjacent sublayers of the cap layer; and a second transistor with a second threshold voltage VT2, comprising a second gate region and a second pair of ohmic contacts disposed outside the second gate region. |
| 地址 |
Cambridge MA US |
