Frequency doubler circuit

摘要

The circuit includes a bistable logic circuit (13) which takes logic state 1 at each state transition of an electrical signal applied to a clock input terminal, corresponding to the circuit input terminal. The bistable logic circuit has at least one output terminal for the circuit output signal and an input return to zero terminal. In an integrator circuit, charging and discharging of a capacitor is controlled by the output of the bistable logic circuit. A comparator at the input terminal receives the charged voltage of the capacitor and the output terminal is connected to the return to zero terminal of the bistable logic circuit.