| 摘要 |
The circuit has an input port (E) taking the incoming CMI binary signals and providing a synchronisation signal. The synchronisation signal (P) is applied to an invertor gate (PW) together with an internal signal (j) to provide a clock signal (h) which has been recovered from the input signal. The clock signal is only generated when the internal and synchronisation signal are at the same logic level. Following the invertor gate, the clock signal is applied to a delay system (RW) applying a delay (t) equal to a half period of the internal signal.
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