| 摘要 |
<p>PURPOSE: To provide a clock signal distribution circuit which stabilizes the synchronous timing operation of an LSI and simplifies the constitution of a control circuit together with reduction of its power consumption. CONSTITUTION: A clock signal distribution circuit has a fan-shaped tree structure 1 of (m+1) stages. An (m) stage consists of a pair of logical gates of (m=2p), where (p) shows an optional natural number. Then only one of odd stages uses an (n) input logical gate 2 among those (m+1) stages (n: natural number of 2 or more). A clock signal is transmitted to a lower stage from a higher stage through almost a centroid position of the cell placement area of every stage, and the fan-out output of the clock signal consists of the same stage and the same load at the gate of every stage. In such a constitution, a clock signal is inputted to one of both input terminals together with a latch enable signal inputted to the other input terminal respectively with an (n) input logical Rate defined as the final stage. As a result, the clock signals of almost same conditions which are controlled by the latch enable signal are outputted to the F/F 4 to 6 from the (n) input logical gate.</p> |
