发明名称 Oberflächenmontierte Lötanordnung von integrierten Schaltungspackungen ohne Drahtanschlüsse
摘要 <p>Described are a process for soldering at least one component having solder bumps to a substrate and a process for forming solder bumps on metal pads of an element, such as an IC package or substrate or both. The bumps are formed by stencil printing solder paste deposits on the metal pads, heating the solder paste deposits to reflow temperature of the solder in the solder paste deposits, and allowing the molten solder in each deposit to coalesce and during subsequent cooling solidify forming the bumps on the metal pads. The bumps are formed by conducting the stencil printing through apertures in an ultra-thick stencil, the apertures having trapezoidal crossection in the plane normal to the broad surfaces of the stencil with the top opening being smaller than the bottom opening and with the walls of the aperture sloping at an angle within a range of from 1 to 45 degrees from the vertical, the solder paste having a low tackiness and high metal loading, and the solder paste deposits covering an area which is equal to or exceeds an area of the metal pad in any ratio between 1.5:1 and 5:1. Bumps formed in this manner lead to the formation of reliable solder joints.</p>
申请公布号 DE69401108(D1) 申请公布日期 1997.01.23
申请号 DE1994601108 申请日期 1994.09.21
申请人 AT & T CORP., NEW YORK, N.Y., US 发明人 DEGANI, YINON, HIGHLAND PARK, NEW JERSEY 08904, US;DUDDERAR, THOMAS DIXON, CHATHAM, NEW JERSEY 07928, US;WOODS, WILLIAM LONZO, JR., KEITHVILLE, LOUISIANA 71047, US
分类号 H01L21/48;H01L21/60;H05K3/12;H05K3/34;(IPC1-7):H05K3/34;B23K3/06 主分类号 H01L21/48
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