发明名称 METHOD AND SYSTEM FOR TESTING ELECTRONIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the number of paths as objects to be tested and to reduce the execution time of a test by selecting test paths covering the positions of combinations between components are selected, adding a circuit whose delay time becomes the delay time close to the cycle time of an electronic circuit to the test paths, and testing the delay time regarding an irregularity in the electronic circuit. SOLUTION: Data on an electronic circuit as an object to be tested is read out from a circuit database 1, and paths covering the portions of combinations of components LSIs are selected. A circuit such as a gate or the like in which the delay time of the selected paths becomes a value at the very limit of a cycle time as a reference is added, and a circuit for an irregularity test is constituted. When the critical path of the objects to be tested is selected, an activation operation is tried, its condition is found out, and an activation circuit is added to the critical path. Circuit data to which a circuit has been added is stored in a circuit database 1', an electronic circuit is manufactured on the basis of the stored data, delay-time test data is generated, and the delay time regarding an irregularity is tested.
申请公布号 JPH0954137(A) 申请公布日期 1997.02.25
申请号 JP19950204479 申请日期 1995.08.10
申请人 FUJITSU LTD 发明人 HIDAKA HISAO
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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