FRAME SYNCHRONISM DETECTION SYSTEM

摘要

PROBLEM TO BE SOLVED: To provide a frame synchronism detection system which is reduced in size and power consumption and rich in flexibility and can be made fast. SOLUTION: The bit sequence of inputted data is rearranged by an SP converting circuit 1 into parallel data and the bit sequence of the inputted data is fetched into a data frequency dividing register 5 with each of frequency- divided clocks outputted by dividing the frequency of a clock input through a frequency divider 4. A synchronism pattern comparing and detecting circuit 2 compares the bit sequence of the data frequency dividing register 5 with the frame synchronism pattern of a frame synchronism pattern comparison memory 21 with each frequency-divided clock and outputs the number of unmatched bits. When they match each other, a frame synchronism detection flag '1' which is previously stored corresponding to the frequency-divided clock is outputted to a clock bit rate pulse generator 6. The clock bit rate pulse generator 6 is a converting means for conversion from the bit rate divided by the frequency two-divider 4 to the bit rate of the clock input.