| 摘要 |
<p>PROBLEM TO BE SOLVED: To demodulate a range gate signal while matching the center thereof with that of each demodulation signal by delaying the O/πand orthogonal O/πdemodulation signals by 1/2 of system clock through a selector when an odd bit pulse width is selected. SOLUTION: One of O/πand orthogonal O/πdemodulation signals from M code generating section 9 and orthogonal O/πgenerating section 10 is inputted to a D flip-flop 12 to produce a signal delayed by 1/2 of system clock. These signal, delayed and not delayed through the D flip-flop 12a, are inputted to a selector 11. The selector 11 receives a pulse width discrimination data from a pulse width data latch 3 and selects a delayed signal from the D flip-flop 12a when an odd bit pulse width is set whereas selects an undelayed signal when an even bit pulse width is set.</p> |
