SELECTIVE THICKENING OF PFET DIELECTRIC

摘要

A complementary metal-oxide semiconductor (CMOS) device and a method of fabricating a CMOS device are described. The method includes forming an interfacial layer in a trench on a substrate in both a p-channel field effect transistor (pFET) area of the CMOS device and an n-channel FET (nFET) area of the CMOS device, depositing a high-k dielectric on the interfacial layer in both the pFET area and the nFET area, selectively forming a first metal layer on the high-k dielectric in only the pFET area, and depositing a second metal layer on the first metal layer in the pFET area and on the high-k dielectric in the nFET area. The method also includes performing an anneal that increases a thickness of the interfacial layer in only the pFET area.

主权项

1. A complementary metal-oxide semiconductor (CMOS) device, comprising:
an n-type field effect transistor (nFET) region, the nFET region including an interfacial layer of a first thickness formed on an nFET substrate; and a p-type field effect transistor (pFET) region, the pFET region including the interfacial layer of a second thickness formed on a pFET substrate, the first thickness being less than the second thickness, wherein the nFET region and the pFET region are regions of a same CMOS device.