COMPACT SELF-ALIGNED IMPLANTATION TRANSISTOR EDGE RESISTOR FOR SRAM SEU MITIGATION

摘要

This disclosure is directed to techniques for fabricating CMOS devices for SRAM cells with resistors formed along transistor well sidewall edges by self-aligned, angled implantation, which may enable more compact SRAM architecture with SEU mitigation, such as for space-based or other radiation-hardened applications. An example method includes implanting a dopant into a doped semiconductor well covered by a barrier, wherein the doped semiconductor well is disposed on a buried insulator and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby fortning a resistor on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type. The method further includes forming a second insulator adjacent to the resistor, removing the barrier, and forming agate layer on the doped semiconductor well, thereby forming a gate adjacent to the doped semiconductor well and the resistor.

主权项

1. A complementary metal-oxide semiconductor (CMOS) device comprising:
a first semiconductor well disposed on a first insulator, the first semiconductor well having a first doping type; a second insulator disposed on the first semiconductor well; a gate disposed on the first semiconductor well; and a resistor disposed on an edge of the first doped semiconductor well, adjacent to the second insulator and in contact with the gate, the resistor having a second doping type opposite the first doping type.