发明名称 PULSE SIGNAL GENERATING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a pulse signal generating circuit capable of generating a pulse signal with a prescribed time width based on a pulse signal received at last even when plural consecutive pulse signals are received as input signals. SOLUTION: A pulse width setting circuit 41 generates a pulse OUT with a prescribed preset time width and provides an output of it based on a change in an input signal NP. A reset circuit 42 outputs a reset signal RS to the pulse width setting circuit 41 when the input signal Np changes at a shorter interval than the set time width by the pulse setting circuit 41 and allows the pulse width setting circuit 41 to output a pulse OUT with a prescribed time width based on the input signal NP received later.</p>
申请公布号 JPH09200009(A) 申请公布日期 1997.07.31
申请号 JP19960007842 申请日期 1996.01.19
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 TERAJIMA AYAKO
分类号 G11C11/41;G11C11/413;H03K3/78;H03K5/13;(IPC1-7):H03K5/13 主分类号 G11C11/41
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