| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a digital PLL circuit operated at a high speed even when lots of load capacitance circuits are provided to a delay circuit by making the area shared by the load capacitance circuits small. SOLUTION: A capacitor C of a load capacitor circuit LC connecting to an inverter of a variable delay circuit of the digital PLL circuit is made cup of a MOS capacitor provided with a switch function. Furthermore, the load capacitor circuit LC is connected in cascade with an output terminal of the inverter to suppress a capacitive component connecting to the inverter low at all times, then the fundamental oscillating frequency of the PLL circuit is designed high. Thus, the capacitor of the load capacitor circuit requires a pattern area nearly a half or below that of a conventional circuit and the required area of the variable delay circuit is reduced.</p> |
