发明名称 Method and apparatus for performing write operations in multi-level cell storage device
摘要 A memory contains a plurality of memory cells that are capable of storing one or more bits of data in each memory cell. The memory stores, in response to a write operation, data corresponding to the write operation in a first set of the memory cells such that each cell of the first set of the memory cells stores a single bit. Thereafter, data from the first set of memory cells are transferred to a second set of the memory cells such that each cell of the second set of the memory cells stores more than a single bit of data. The write operation to the first set of cells is executed in a foreground operation, and in a subsequent background operation, data from the first set of memory cells are transferred to the second set of memory cells. The memory cells are non-volatile flash electrically erasable programmable read only memory (EEPROM) cells, and therefore require erasure before programming. Typically, memory cells are reclaimed in a background operation. However, if not enough memory cells are available for a write operation, then a set of memory cells are reclaimed in a foreground operation, and more than one bit of the data are stored in the reclaimed memory cells.
申请公布号 US5671388(A) 申请公布日期 1997.09.23
申请号 US19950433614 申请日期 1995.05.03
申请人 INTEL CORPORATION 发明人 HASBUN, ROBERT N.
分类号 G06F12/02;G11C11/56;(IPC1-7):G06F12/02 主分类号 G06F12/02
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