| 摘要 |
<p>PROBLEM TO BE SOLVED: To obtain a pulse delaying device in which a pulse delaying circuit which can accurately divide input clock signals in one period into 2<m> (m: a positive integer of >=3) phases can be constituted, designed, and controlled easily in, for example, an IC and the error which occurs at the time of dividing the phase becomes the minimum. SOLUTION: The input signals of variable pulse delaying circuits 2-2 having delay amount of 3To/8 are delayed against the period To of an input clock signal CK by 3To/8 by cascade-connecting the circuits 2-2. The delay amounts are controlled by obtaining the product of the input signal of the first-stage delaying circuit 2-2 and the output signal of the last-state delaying circuit 2-2 by means of an EX-OR 7-2 and inputting the product to a charge pump circuit 302 through an OR 6-2.</p> |
