III-V field effect transistor (FET) with reduced short channel leakage, integrated circuit (IC) chip and method of manufacture

摘要

Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer and a buried layer. A gate stack is formed on each FET location. Source/drain regions are sub-etched at each said gate stack. The sub-etched source/drain regions define a channel under each said gate stack. A layered source/drain is formed in each sub-etched source/drain region.

主权项

1. A method of forming Field Effect Transistors (FETs), said method comprising:
defining FET locations in a surface layer of a layered semiconductor wafer, wherein said surface layer is a III-V semiconductor layer; forming a gate stack on each FET location; sub-etching source/drain regions at each said gate stack, the sub-etched source/drain regions defining a channel under each said gate stack; and forming a layered source/drain in each sub-etched source/drain region, forming said layered source/drain region comprising:
growing a first III-V semiconductor layer in said sub-etched source/drain regions,growing a second III-V semiconductor layer on said first III-V semiconductor layer, said second III-V semiconductor layer being lattice-matched to said channel, andgrowing a third III-V semiconductor layer on said second III-V semiconductor layer.