| 摘要 |
PROBLEM TO BE SOLVED: To remarkably shorten the time required for providing synthetic data by matching the phases of data of respective systems based on a synthesizing clock, synthesizing these data later, decoding the synthetic data provided by synthesization and outputting them as decoded signals. SOLUTION: This in-phase synthetic reception circuit 10 generates the synthesizing clock at timing matched with all the received signals of respective systems from reproducing clocks C1 and C2 extracted by received signals D1 and D2 of respective systems. Thus, the phases of demodulated data D3 and D4 of respective received signals are matched based on the synthesizing clock without turning the phases of respective systems into in-phase state for each system. Further, by synthesizing the demodulated data D3 and D4 of respective systems, synthetic data D5 are generated, by decoding these synthetic data D5, circuit configuration required for synthesizing clock generation is simplified, production cost is reduced and processing time is remarkably shortened. |
