High Voltage Vertical FPMOS Fets

摘要

Semiconductor power devices such as vertical FPMOS are described having a plurality of trenches formed at a top portion of a semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction. Each trench has sidewalls generally perpendicular to a longitudinal direction of the trench and extending downward from a top surface to a trench bottom. Gate electrodes and source electrodes are positioned in the trenches. Higher voltage resistance is achieved while increasing current by spacing the trenches and providing particular dopant levels to allow more even distribution of depletion layer regions across a power device during use.

主权项

1. A semiconductor power device disposed in a semiconductor substrate, comprising:
trenches having defined widths formed at defined intervals perpendicular to and across a top portion of the semiconductor substrate extending laterally across the substrate and extending into an epitaxial layer; base regions located outside the trenches; trench source electrodes inside the trenches; and gate electrodes inside the trenches positioned between the trench source electrodes and the base regions, wherein a ratio of the intervals between trenches and the widths of the trenches is from 1.0 to 2.5.