THREE DIMENSIONAL NAND DEVICE WITH CHANNEL CONTACTING CONDUCTIVE SOURCE LINE AND METHOD OF MAKING THEREOF

摘要

A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line.

主权项

1. A memory block, comprising:
a substrate; a conductive source line that extends substantially parallel to a major surface of the substrate; an array comprising at least one row of monolithic three dimensional NAND strings; a first dielectric filled trench located on a first side of the array; a second dielectric filled trench located on a second side of the array opposite to the first side of the array; a first source electrode located in the first dielectric filled trench and extending substantially perpendicular to the major surface of the substrate, wherein a bottom portion of the first source electrode contacts the conductive source line; a second source electrode located in the second dielectric filled trench and extending substantially perpendicular to the major surface of the substrate, wherein a bottom portion of the second source electrode contacts the conductive source line; and a plurality of drain lines located over the array; wherein:each NAND string comprises a semiconductor channel extending substantially parallel to a major surface of the substrate, a tunnel dielectric located adjacent to an end portion of the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region, a source side select gate electrode, a gate insulating layer, a drain side select gate electrode, and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate;the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;
the conductive source line is continuous in the array; and at least one of a bottom portion and a side portion of the semiconductor channel contacts the conductive source line.