STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND ASSOCIATED METHODS

摘要

A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

主权项

1. A semiconductor die assembly, comprising:
a package support substrate; a first semiconductor die having a peripheral region and a stacking site; a plurality of second semiconductor dies arranged in a stack and mounted to the stacking site of the first die; a metal casing having first portion and a second portion, the first portion being attached to peripheral region of the first die and having an inner surface, the inner surface being spaced apart from the stack of second dies and extending upward, and the second portion enclosing the stack of second dies; and an underfill material between the stack of second dies and the first portion of the casing, wherein a portion of the underfill material engages the inner surface of the first portion.