| 摘要 |
PROBLEM TO BE SOLVED: To easily reduce the circuit scale and increase the multiplication speed by forming a partial product arithmetic circuit which finds the partial product of only bits of 1 of a multiplicator and a multiplicand. SOLUTION: A conversion rule 2 converts a multiplier 191 which multiplies a multiplicand X with bit width (n) by a multiplicator Y with bit width (m) and outputs their product P into a circuit consisting of multipliers 192 and 193 which multiply the multiplicand X by the low-order K bits Y1 and high-order (m-K) bits Y2 of the multiplicator Y to find their partial products P1 and P2 and a circuit which adds those partial products P1 and P2. Thus, the conversion for dividing the multiplicator Y is performed, so the number of bits of 1 becomes less than that of the original multiplicator Y and the circuit is generated which finds the partial products P1 and P2 of only the bits of 1, so that the number of the partial products and the number of logic stages of circuits for finding the sum of the partial products can be suppressed small. |
