| 摘要 |
PROBLEM TO BE SOLVED: To execute highly accurate inter-signal skewness reduction while keeping a circuit scale small by separately providing a circuit for reducing the large skewness of clock signals and the circuit for reducing the small skewness between signals. SOLUTION: A skewness reduction circuit 10 is provided with an RF(rise/fall) skewness reduction circuit 11, an inter-signal skewness reduction circuit 12 and a clock buffer circuit 13. The RF skewness reduction circuit 11 reduces the rising/falling skewness of the clock signals CLK and the signals A by the clock signals CLK and outputs the signals A1 for which the rising/falling skewness of the signals A is reduced and the clock signals CLK1 for which the rising/falling skewness of the clock signals CLK is reduced. The inter-signal skewness reduction circuit 12 receives the clock signals CLK3 for which the clock signals CLK1 are delayed in the clock buffer circuit 13 and reduces the skewness between the clock signals CLK3 and the signals A1. |
