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发明名称
SEMICONDUCTOR INTEGRATED CIRCUIT, VOLTAGE CONTROLLED DELAY LINE, DELAY LOCKED LOOP, SELF-SYNCHRONOUS PIPELINE DIGITAL SYSTEM, VOLTAGE CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP
摘要
申请公布号
JPH1127116(A)
申请公布日期
1999.01.29
申请号
JP19970176867
申请日期
1997.07.02
申请人
OMI TADAHIRO;CANON INC
发明人
OGAWA KATSUHISA;OMI TADAHIRO;SHIBATA SUNAO
分类号
G11C11/4076;H03H11/26;H03K3/03;H03K3/354;H03K5/00;H03K5/13;H03L7/081;H03L7/099;(IPC1-7):H03K5/13
主分类号
G11C11/4076
代理机构
代理人
主权项
地址
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